A Real-time Decision Diagram for Timing Analysis and Synthesis

In this paper, we introduce an efficient real-time decision diagram, TBF BDD, characterizing both logical functionality and timing information of circuits. In contrast to the conventional timing methods that discretize time, this decision diagram permits real and continuous time and is applicable to both combinational and synchronous sequential circuits. First, we demonstrate how circuits can be represented functionally and temporally with TBF BDD’s. Then, we prove that TBF BDD’s have a canonical representation, i.e. two circuits have exactly the same timing behavior if and only if their TBF BDD’s are identical (or graphically isomorphic), and construct algorithms to transform TBF BDD’s to this canonical representation. Further, we derive algorithms for manipulating TBF BDD’s and demonstrate their efficiency by showing that these operations have complexities similar to those of binary decision diagrams. Becauseof the many similarities between BDD’s and TBF BDD’s, existing techniques in analysis as well as synthesis may be extended into the timing domain with TBF BDD’s. Finally, we apply TBF BDD’s to the exact computation of delays of combinational circuits, and compare sizes of BDD and TBF BDD with experimental results from ISCAS benchmarks.